The present invention relates to an error control system and, more particularly, to an error control device suitably used for digital recording optical disks (including magnetooptical disks and phase change disks), digital recording hard disks, digital recording VTRs (Video Tape Recorders), and the like.
In conventional digital recording disk apparatuses, digital recording VTRS, and the like, error correction codes and error detection codes are used. They are all fixed-length codes. For example, in a CD (Compact Disk), 4-byte Reed-Solomon codes are added to an internal code in units of 28-byte data, and 4-byte Reed-Solomon codes are added to an external code in units of 24-byte data.
In a DVC (Digital Video Cassette) for a digital VTR, 8-byte Reed-Solomon codes are added to an internal code in units of 77-byte data, and 11-byte Reed-Solomon codes are added to an external code in units of 138-byte data.
In the optical disk recorder (VF-200) developed by the present applicant, 16-byte Reed-Solomon codes are added to an internal code in units of 174-byte data, and 8-byte Reed-Solomon code codes are added to an external code in units of 128-byte data.
These codes are all fixed-length codes whose data consists of predetermined numbers of bytes. Similarly, error detection codes such as CRCCs are all fixed-length codes whose data consists of predetermined numbers of bits.
Since the above CD, DVC, and optical disk recorder (VF-200) handle fixed-length data as non-compressed video/speech signals, fixed-length codes are suitably used.
In recording apparatuses handling compressed video/speech signals, since variable-length data is used, fixed-length codes may pose a problem in terms of compatibility.
Assume that a 1-frame video signal is constituted by 720 (pixel).times.480 (line); one block, 8 (pixel).times.8 (line); one macroblock, a 4-block Y signal, i.e., 16 (pixel).times.16 (line); and one slice, 45 macroblocks in the horizontal direction, i.e., 720 (pixel).times.16 (line).
FIG. 18 shows an example of how CRCC (Cyclic Redundancy Check Code) error detection codes are added to variable-length codes. FIG. 14 shows an example of the arrangement of a known CRCC register. Referring to FIG. 14, reference numeral 1 denotes a delay element; and 2, an adder.
As shown in FIG. 18, the code amount of 1-slice data after compression changes. For example, the code amount changes to 400 bits or 250 bits. In such a case, if fixed-length error correction and detection codes are used, an error correction code sequence or an error detection code sequence cannot be matched with a slice. As a result, an error in a given sequence propagates to the next slice, and the efficiency of correction/detection processing deteriorates. If, however, variable-length codes can be used, an error correction code sequence or an error detection code sequence can be matched with a slice, the efficiency of correction/detection processing improves.